Is well known that applications requiring digital signal processing are expanding tremendously. For instance, applications requiring voice, or image signal processing for further transmission over digital networks or storage . . . , are obviously becoming commonly requested.
Most of these applications do require filtering (convolution) or correlation operations which are fairly high processor computing power consumers. Signal processor architectures have therefore been looked for, which would optimize available computing power versus processor size and power supply requirements.
For instance, taking into account the fact that the above mentioned convolution/correlation operations do involve repetitive digital multiplications, a processor architecture has been proposed wherein a multiplier is connected in parallel over the processor Arithmetic and Logic Unit (ALU) input and then feeds multiplication results back into ALU, to then store the result in either one of two accumulators connected to get the ALU output.
Alternatively switching ALU output from one accumulator to another, already improved the processor operating cycles.
For further details on both techniques, one may refer to G. Ungerboeck et al, "Architecture of a DSP" in IBM Journal of Research and
Development, Vol. 29, N. 2, April 1985. Yet further improvements are still being looked for to keep proceeding toward signal processor optimization.